| The advent of mobile wireless communications has generated increased demand for long lasting portable device operation, and consequently, system power dissipation has become an important design metric. This dissertation presents a design methodology for reducing the power consumption of several critical aspects of wireless communication system while achieving a desired level of performance. In particular, the design methodology focuses on the architectural and algorithmic optimization of synchronization techniques and decoding algorithms. First, a low-power multiplier design methodology for DSP and communication system applications is proposed. Then, the front-end digital components such as a matched filter and a fast Fourier transform, which are integral part of the demodulation and synchronization, are optimized for low-power. Also, a low-complexity synchronization technique for a hybrid spread-spectrum system is developed and analyzed which supports frequency hopping and variable spreading gain transmission. In addition, an efficient synchronization scheme is developed with low-complexity physical realization for multi-carrier spread-spectrum system. This dissertation also discussed the importance of channel coding and presented a low-complexity architecture and its low-power VLSI implementation for a turbo-code. Finally, a system level power optimization method is presented where the selection of algorithms and choice of accuracy are determined to minimize the overall power dissipation through power-performance tradeoff analysis. |
