| Power management is an important design consideration in VLSI systems. The energy consumption of a chip has a direct impact on reliability, packaging costs, cooling costs, and battery life. While this is an important consideration, it is often secondary behind performance and time to market. Hence, modifying a circuit to reduce power consumption with minimal impact on performance and design time is an important task.; In this dissertation, a method is presented for reducing power consumption in combinational logic circuits by reducing spurious transitions caused by glitching. Using a well known technique called signal gating, logic elements are inserted into a circuit to prevent spurious transitions from propagating through the circuit and dissipating unnecessary power. This is accomplished by extending two existing techniques. The first uses the transition retaining barrier, which is a logic barrier that prevents spurious signals from propagating further along the path. The second is the use of an efficient gate, called a freeze gate, to implement the barriers. An algorithm is presented for systematically placing the barriers along the path using a divide and conquer method by repeatedly inserting them halfway between the primary inputs, primary outputs, and barriers inserted during previous passes. Iterative simulations determine the effect of the changes on switching activity, so the designer can select the optimal configuration. In previous work, iterative simulations were often avoided due to their long runtimes. What makes this approach unique is that when a barrier is inserted, the design is evaluated using a fast simulation, which is a gate-level simulation under a lumped delay model that quickly estimates the transition count by simulating the circuit and only monitoring the switching activity on the connections between modules. |
