| In point-to-point parallel links, the design goals are to increase the bit rate per I/O and integrate a large number of I/Os in the system. Voltage and timing error sources limit the performance of a link and affect its robustness. The voltage and timing noise sources unique in parallel links, such as inter-signal timing skew and inter-signal cross-talk, impose greater challenges as the performance increases. Mass integration requires low cost per I/O and the use of low-cost solutions, such as using cheaper electrical components, single-ended signalling, and simultaneous bidirectional signalling, further increases the voltage and timing noise.; In this research, we characterize, both analytically and experimentally, the voltage and timing noise sources in high-speed single-ended and simultaneous bidirectional links. We built an 8-bit single-ended, simultaneous bidirectional parallel link transceiver test chip in a 0.35μm CMOS process which allows full-range per pin skew compensation. The links achieve a bidirectional data rate of 2.4Gbps/pin with a BER less than 8 × 10−15. The chip dissipates less than 1W total power from a 3.3V supply, and occupies a die area of 1.7 × 3.8mm2.; We demonstrate that per pin skew compensation improves receiver timing margins in high-performance parallel links, and the cost overhead depends largely on the range and accuracy of the compensation desired. We compare different receiver timing recovery clock generation strategies, and the results show that the receiver clock generation delay makes tracking the high-frequency jitter of a source-synchronous reference clock difficult, and hence using a stable clock source is the best strategy. Low-frequency phase drifts in the interface signals can be compensated by a periodic calibration, making the source-synchronous reference clock unnecessary.; We also demonstrate that single-ended and simultaneous bidirectional links are viable alternatives to the traditional differential and unidirectional systems. They allow significant savings in wires and pins for the same bandwidth, and the additional voltage noise sources, while significant, can be managed by careful design in circuits and in packaging. |
