Design Of High Reliability SiC MOSFET Driver Circuit

With the development of automobile electronic and power electronic products market,the market demand of power switch devices and driving chips is expanding day by day.However,the volume of electronic equipment is reduced generation by generation,and the application environment is more and more harsh.The performance requirements of power switch devices and their driver chips are also increasing,which is mainly reflected in the requirements of higher efficiency,higher power density and higher reliability.The third generation power semiconductor SiC is favored by many manufacturers because of its high-speed,high power density,high temperature resistance and other characteristics.The high speed,high voltage and high current of SiC Power MOSFET decides that its driver chip needs to have complete protection function to prevent the failure of SiC Power MOSFET due to non ideal external factors.The core technology of SiC Power MOSFET driving technology is mainly to improve the anti position dv/dt ability of SiC Power MOSFET(that is,when the change of dv/dt at the drain of the power transistor is coupled to the power transistor gate through Miller capacitance,the inhibition ability of the coupling),the transient and steady driving ability of SiC Power MOSFET and the abnormal state protection ability of SiC Power MOSFET.The above core technologies can be embodied in high voltage and high frequency applications of automotive electronics and industrial electronics.In this paper,a dynamic Miller clamp circuit and a negative pressure shut-off function are proposed for the above core technology.The circuit realizes 150 V / ns higher anti position dv/dt capability when the DC voltage of the SiC Power MOSFET is 1200V;a dual floating power rail circuit is proposed,which means that when the power supply voltage of the driver chip is-8V to 20 V,a negative floating power rail of-3V and a positive floating power rail of 15 V are generated to realize the driving of thin gate oxide MOSFET and avoid the use of thick gate oxide devices,thus ensuring the large current drive capability of 4A,the transient delay of 8ns(1n F load capacitance)and the transmission delay of 20 ns.A complete under-voltage protection function is proposed,including the chip bus under-voltage protection function with 1V hysteresis window and the under-voltage point can be cheated out of the chip,and 5V LDO under-voltage protection function;A proposed over temperature protection function realizes over temperature protection triggered by 150°C,with a hysteresis window of 25°C,so as to ensure that the silicon-based driver chip will not fail due to high temperature;A proposed over-current protection function,realizes the leading edge blanking function of 520 ns and the over-current point can be configured outside the chip.The above functions are all on-chip integration,and the integrated chip is equipped with a reference,a low-pressure difference linear regulator,a current bias,and an on-chip integrated negative pressure charge pump.The circuit design,simulation verification and chip layout design of the driver chip are completed in the 0.35 ?m BCD process.The simulation results show that the transmission delay,transient drive delay and peak drive current of the driver chip all meet the theoretical design values and meet the drive requirements of SiC Power MOSFET.