| The progress of RF CMOS design so far has been mainly focused on the receiver. The transmitter, especially the power amplifier (PA), has received very limited attention. To achieve a complete radio system on a chip using CMOS technology, it is essential to demonstrate that the power amplifier can be built in this technology. In this dissertation, we have demonstrated such capability by designing a 1.5W class F power amplifier using a 0.2-μm standard CMOS technology.; Since the CMOS process is targeted for digital applications, the models provided by foundries do not meet the requirements for RF simulation. To address this issue, we have developed our own RF CMOS model for this project. During the development of the model, we have developed a new method for extracting the parasitic gate resistance and a distributed junction diode and substrate network to improve the high frequency model accuracy.; Designing RF power amplifiers for realization using deep sub-micron CMOS technology faces special technical challenges that are not present in the receiver design. We have developed a method to determine the optimum operating condition that addresses the high knee voltage issue with CMOS devices. Low oxide breakdown voltage has been one of the major concerns for designing CMOS PAs. Circuit techniques that greatly reduce the device stress are presented. A driver design that takes advantage of the CMOS technology advance and further reduces the device stress is discussed.; The results of the CMOS PA research are summarized and compared with previous publications. Since the push-pull configuration is used, a balun transformer is needed to interface between the PA and the antenna. To eliminate this balun, a differential antenna has been designed and fabricated. The measurement results for this antenna are compared with a standard antenna approach.; Harmonic reduction and efficiency enhancement techniques are also discussed. We have developed a new type of power amplifier architecture as an alternative choice for class F amplifiers. Improved harmonic performance is achieved with this new amplifier. The requirement of maintaining high efficiency with reduced output power is discussed. Such a requirement stems from the power control algorithm implemented in most of the cellular systems today. By dynamically controlling the load line, high efficiency can be achieved across a wide range of output power. |
