Design and analysis of double-gate CMOS for low-voltage integrated circuit applications, including physical modeling of silicon-on-insulator MOSFETs

This dissertation mainly focuses on analysis and design of scaled double-gate (DG) silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) for low-voltage integrated circuit (IC) applications; related physical modeling of fully depleted (FD) and partially depleted (or non-fully depleted, NFD) SOI MOSFETs is presented as well. Achieving the ballistic-limit current in Si MOSFETs is discussed based on a theoretical analysis of the fundamental limit current. The study considers measured data of extremely scaled bulk-Si and SOI CMOS devices, and Monte Carlo-simulated data of 25 nm bulk-Si and DG CMOS devices, and concludes that, for controlled off-state current, only an optimally designed DG structure could yield a ballistic-limit on-state current. Because off-state current in SOI MOSFETs is one of the major issues for contemporary low-voltage/low-power IC applications, gate-induced drain leakage (GIDL) and reverse-bias junction tunneling currents, which can significantly govern off-state current, are physically analyzed and incorporated in the University of Florida SOI (UFSOI) MOSFET models. The viability of FD/SOI CMOS is examined for deep-submicron (<0.1 μm) channel lengths, suggesting that the DG MOSFET is the structure needed for scaling the FD/SOI technology. The DG MOSFETs, with either symmetrical or asymmetrical gates, are strong candidates for future CMOS IC applications due to the charge coupling of the two gates via the thin, fully depleted silicon film body. Comparison of asymmetrical and symmetrical DG devices is comprehensively done for the first time. Numerical device-simulation results, supplemented by analytical characterizations, are presented to argue that asymmetrical DG CMOS, using n+ and p+ polysilicon gates, can be superior to symmetrical-gate counterparts for several reasons. The GIDL effects, which tend to be more severe in the asymmetrical DG device, are analyzed and shown to be controlled via optimal design. Simulation-based design and analysis of 25 nm DG CMOS are presented, showing feasibility of extremely scaled DG MOSFETs, even when imperfectly fabricated. Quantum-mechanical issues and quasi-ballistic transport are considered in the simulation-based design of 25 nm DG CMOS; circuit performance projections suggest that optimal DG CMOS is far superior to the bulk-Si counterpart technology.