| In spite of recent technology advancements in design automation, hardware design verification is still challenging work. Among various design stages, verification of register-transfer-level (RTL) design is often left to a designer's insight and judgement due to the lack of tools and the availability of formal specification at, this level.; The objective of this research is to propose a more reliable and effective RTL design verification system that calculates more meaningful coverage value and accelerates the verification simulation process.; An important issue in RTL hardware verification is to check for correct implementation of specified functions and to determine the presence of an error. Code-level coverage is often used to measure the success in verification at this level. However, existing code-level coverage inaccurately estimates the verification result by considering only the excitations of functional blocks. While it may be impossible to measure the correctness of a design using coverage measure, coverage analysis can be extended to include control attributes such as conditions in a design (e.g. modified condition checking). Further, it is important to correctly evaluate functions and to monitor the effects at the output ports when checking the conditions.; This research includes a new coverage analysis approach that evaluates the excitation-state of conditional expressions and associated variables in addition to the code-level coverage. The observation-based coverage analysis approach ensures checking of correct functionality, resulting in increased error detection resolution.; Validation of the approach is conducted using a commercial ATPG tool and a gate-level single stuck-at fault test vector set, which has known observability property. Application results from ITC'99 VHDL benchmark designs and the validation experiment results demonstrate the significance of the proposed approach, showing a better correlation between the new coverage rate and mutant test score than that of existing excitation-only coverage metrics.; This research also proposes verification simulation acceleration using a code-perturbation technique. Experiment results show that additional coverage value for a fixed verification time, or less compute-cycles to get the same state coverage level is achieved with the proposed approach over ordinary code-based simulation.; The implemented verification system, which is based on a Verilog programming language interface, shows good verification performance with less user interference, fast coverage calculation, and less system overhead. |
