| From mobile computing to wireless applications, Polys&barbelow;ilicon-O&barbelow;xide-N&barbelow;itride-O&barbelow;xide-S&barbelow;ilicon (SONOS) Nonvolatile Semiconductor Memories (NVSMs) meet the memory challenges of the microelectronics world. With respect to scaling programming voltage and memory cell size, SONOS shows advantages over traditional ‘floating gate’ Flash technology.; Scaling the programming voltage, while still maintaining 10-year data retention time, presents a big challenge for SONOS researchers. In this dissertation, we introduce the design, scaling, fabrication and characterization of SONOS NVSM devices. We describe progress in the design and scaling of SONOS nonvolatile memory devices. We have successfully realized −9V/+10V (1ms) programmable SONOS devices ensuring 10 years retention time after 107 Erase/Write cycles at 85°C through scaling and fabrication process optimization. Deuterium anneals, applied in SONOS device fabrication for the first time, improve the endurance characteristics over traditional hydrogen or forming gas anneals. We optimized the fabrication process based on other researchers' finding, such as the tunnel oxide growth temperature, ONO LPCVD deposition conditions. We present scaling considerations and process optimization along with experiments and SONOS device characterization.; Moreover, we have discovered a new retention degradation mechanism, which occurs during an ‘over-erase’ of the SONOS device. We attribute this degradation to a non-uniform stored charge distribution in nitride storage layer. A theoretical analytical model has been developed and simulation results agree with experimental observations. In our research, we offer suggestions to improve the retention reliability.; In addition, a Field Programmable Gate Array (FPGA)-based measurement system has been designed and constructed for the dynamic characterization of SONOS nonvolatile memory devices. The attractive features of this measurement system design lies in the cost-effectiveness and flexibility of the test pattern implementation, fast readout of the memory state, low power, high precision determination of the device threshold voltage, and perhaps most important, minimum disturbance, which is indispensable for nonvolatile memory characterization. This system has been employed in the characterization of SONOS NVSM devices and arrays.; In this dissertation, we present SONOS device design, fabrication, process optimization, measurement circuit design and electrical characterization. The results of our research indicate that SONOS NVSMs are ready to compete with the existing ‘floating gate’ NVSM technology for a wide range of applications. |
