Uniform and localized charge-trapping in SONOS nonvolatile memory devices

Polysilicon-oxide-nitride-oxide-silicon (SONOS) devices are promising for next generation non-volatile semiconductor memories (NVSMs), due to their low-voltage/low-power operation and low cost integration with standard CMOS technology. In order to exploit these advantages, retention loss of SONOS devices that uses uniform charge injection with tunneling through a thin tunnel oxide, as well as endurance issues of SONOS (NROM) devices that utilize localized hot carrier injection through a thick bottom oxide, are investigated in this work.; We have developed an analytical retention model for scaled SONOS devices in the excess electron state, which includes band-to-band tunneling and thermal excitation as charge loss mechanisms. Simulated retention characteristics with this model agree well with measured data at temperatures from 22°C to 225°C. Guided by this model, we have fabricated SONOS devices with a 2.5 nm thick tunnel oxide and modulated (in space and energy) trap density in the charge-storage nitride. These devices show good retention, speed and endurance performance.; We have also investigated localized charge-trapping in SONOS with hot carrier injection for erase/write. The spatial profile of the localized interface damages and charge trapping in SONOS devices under channel hot electron injection are obtained with a charge-pumping technique. Experimental erase/write speed and retention characteristics suggest lateral migration of localized charges is a major reliability issue for these devices. TCAD simulations reveal subsurface conduction is responsible for the threshold voltage roll-off and subthreshold swing degradation in the SONOS devices with localized charge-trapping. A novel localized ONO structure on a SOI substrate is proposed and demonstrated with 2-D device simulations to suppress lateral charge migration and subsurface conduction. In addition, experimental result show a novel SONOS device with hot hole injection for write and gate tunneling for erase can achieve high charge injection efficiency and improved data retention due to reduced misalignment between electron/hole trappings.