Compensation of delta-sigma modulators: Stabilization, signal restoration and integrated circuits

We propose novel architectures and techniques for the stabilization of continuous-time delta-sigma modulators, the on-line restoration of corrupted oversampled data, and the implementation of high speed delta-sigma modulators in complementary metal-oxide semiconductor integrated circuit technology. Specifically, the contributions of this work are threefold: (1) A novel architecture for the stabilization of continuous-time delta-sigma modulators of arbitrary order is proposed. The approach features a guarantee of stability under certain assumptions and accommodates quantizers incorporating any number of levels and dithering. An estimation method to predict long-term SNR performance of the stabilized delta-sigma modulator is provided. We show that first-order noise-shaping can be achieved. (2) New measures for the management of instability in delta-sigma modulation are proposed. Digital state estimation techniques based on observer theory adapted to delta-sigma modulation are developed and simulated. Restorative algorithms suitable for multiplier-free digital implementation are also provided and simulated. Significant SNR recoveries are shown to be possible. (3) A compensated fifth-order single-bit continuous-time delta-sigma modulator integrated circuit for analog-to-digital conversion is designed, laid-out, fabricated (in a 0.35-micron CMOS technology) and tested. The basic operation of our soft-resetting technique is demonstrated in steady-state. Nominal performance of 56-dB SNDR and 51-dB DR in a signal bandwidth from 100–500 kHz is achieved. The presence of a non-ideal do offset is discussed and a possible remedy is proposed. The main purpose of the IC is for demonstrating that advanced switching control techniques can be implemented in a practical fashion. The chip does not represent a contribution to the state-of-the-art in nominal SNDR and DR modulator performance.