Analysis and design of high-speed high-resolution analog-to-digital converter

A pipeline ADC (Analog-to-Digital Converter) architecture is proposed. The ADC is composed of a unique first stage and a conventional second stage. A track-hold and an operational amplifier have been proposed to be used in the ADC system.; The first stage is implemented in the transistor level. It can generate an analog residue at 10-bit accuracy level with 100MHz sampling frequency. The track-hold has a 14-bit linearity with 13MHz input frequency and 100MHz sampling frequency. The power supply is +/−1.65V for the overall system. The circuits are designed using a 0.18 μm digital CMOS process and the layout is finished.; Two chips have been fabricated and tested. The track-hold chip consumes 23.76mW power from a +/−1.65 V power supply. The track-hold has 11-bit resolution. The ADC chip is functional with the proposed track-hold.; The results proved the research ideas.