| This dissertation describes high temperature memories as part of the design for 275 °C HC11 microcontroller and 200 °C LEON3 processor using the 0.5um Peregrine SOS CMOS technology. The memories having been designed include: a 4K on-chip SRAM, 512byte on-chip ROM, 4K SPI-SRAM, 2K SPI-ROM , 2K x16 off-chip SRAM, 128 x 32 cache , 32 x 32 cache, and SRAM design with Encounter support. The 4K SPI-SRAM testing and 2K SPI-ROM confirmed operations across room to 275 °C. The LEON3 testing confirmed operations across room to 200 °C including 128 x 32 cache and 32 x 32 cache. With testing analysis, good candidates for error sources of memory failure were found and memory yield can be improved for future memory designs. The error sources are believed to be mainly the silicon defects and/or strong (leaky NMOS) transistors, and Metal2 shorts. The developed methodologies presented are essential for the microprocessor and memory designs across process and temperature corners. Data for ION and IOFF, threshold and mobility was developed with temperature. High temperature 3.3V cell libraries were developed for the LEON3 and HC11. The memories were designed with aid from the measured data, addressing write and read stability in the context of floating body effect, kink effect, shrinking ION/IOFF currents. Especially a novel 6T PMOS SRAM cell and a stacked-NMOS sense amp were designed to solve these issues. The LEON3/HC11 was placed and routed with the standard cell library and characterized memories. Finally, SRAM design with Encounter support has been demonstrated to be a fast time to market memory design solution. |
