Memory-centric low power digital system design

In today’s era of pervasive mobile computing and wireless communication on portable devices, power dissipation of digital systems is of great practical importance. Co-optimizing algorithm and architecture of multimedia signal processing, which is a ubiquitous application in portable embedded systems, to meet performance requirements with minimal possible power consumption is highly desirable and meanwhile challenging.;Although continuous technology scaling can naturally reduce the computation power consumption in digital signal processing systems, power consumption of memory subsystem does not ride the wave since the capacity of memory integrated in systems becomes larger and larger in order to fulfill the ever increasing performance requirements. Thus, optimization of memory subsystem and its impact on computational logic design can lead to significantly more energy-efficient digital systems. The main contributions of our research focus on the methodologies and corresponding approaches on low power digital system design by incorporating the entire memory hierarchy into the overall system optimization.;First, we investigate the three-dimensional (3D) integrated computing platforms that stack high-density DRAM die(s) with a logic die for memory-hungry applications such as multimedia signal processing. We consider the design of motion estimation accelerator under a 3D logic-DRAM integrated heterogeneous multi-core system framework. One specific DRAM organization and image frame storage strategy geared to motion estimation are proposed. This design strategy can seamlessly support various motion estimation algorithms and variable block size with high energy efficiency.;In mobile devices, video processing is one of the most energy-hungry tasks, and DRAM image data access energy consumption becomes increasingly dominant in overall system energy consumption. We develop domain-specific data processing techniques that exploit unique image data access characteristics to improve DRAM energy efficiency. We apply three simple yet effective data manipulation techniques that exploit image data spatial/temporal correlation to reduce DRAM image data access energy consumption, and propose a heterogeneous DRAM architecture that can better adapt to unbalanced image access in most video processing to further improve DRAM energy efficiency.;Finally, motivated by the observation of limited power source and abundant flash memory capacity in embedded and mobile devices, we incorporate NAND flash memory into video coding system optimization. We present a joint source coding, channel coding, and flash memory channelization design framework to obtain optimized trade-off among energy consumption, bit rate, and end-to-end distortion (i.e., optimal E-R-D trade-off space). The optimal E-R-D trade-off space enables embedded and mobile devices to cohesively optimize the video source coding and data storage system operations subject to run-time power source, storage capacity, and/or distortion constraints. xii.