| On-chip electrostatic discharge (ESD) protection circuits are essential in modern integrated circuits for reliability and yield purposes. However, ESD protection devices are not well understood because they work in high current region where models designed for normal operating semiconductor devices are no longer applicable. Hot carrier effects and thermal effects become important for device characteristics analysis. Furthermore, since ESD protection devices are off during normal operation, an effective trigger mechanism is required for them to be turned on reliably and quickly when an ESD event takes place. This usually translates to a voltage snapback seen in the I-V curves and thus a negative differential resistance (NDR) region. ESD protection device models must be able to capture this kind of behavior and at the same time be able to avoid simulation convergence problems.; In this dissertation, extensive results are presented on characterization, design, and modeling of on-chip ESD protection devices. Specifically, simulator-independent circuit-level compact models for ESD protection NMOSFETs and diodes are developed using the Verilog-A language. Model confirmations are obtained through experimental data of a 0.6-mum, and a 0.13-mum CMOS technology. Small-signal and large-signal models are provided to ensure accurate ac and transient simulation. Improved avalanche multiplication factor equations are used to avoid convergence problems. Key modeling parameters are analyzed and important elements identified for accurate capture of the trigger voltage. Various trigger mechanisms are then studied to further understand the NMOS transient snapback behavior. Compact models of the on-resistance are proposed to incorporate the self-heating effect. Investigations on the turn-on behaviors of ESD protection MOSFETs and diodes reveal clear voltage overshooting with the help of an improved VFTLP (Very Fast Transmission Line Pulsing) system. Next, the ESD robustness of a 0.13-mum CMOS technology is carefully evaluated with design considerations given. Last, design techniques of RC-triggered, MOSFET based power clamps are discussed. A compact, timed-shutoff power clamp is proposed for area reduction and performance improvement. |
