On the analysis, design, and modeling of electrostatic discharge protection devices for analog and radio-frequency integrated circuits

In this dissertation, we discuss current and future issues regarding the protection of analog and radio-frequency (RF) integrated circuits (ICs) from electrostatic discharge (ESD) events. We begin with a brief overview of ESD phenomena, and a discussion of the transmission line pulsed (TLP) measurements used to characterize on-chip protection devices.; We apply elementary microwave theory to the design of a new TLP system that yields more accurate, reliable, and functional measurements. Specifically, the use of matched attenuators eliminates multiple reflections within the system in the presence of nonidealities, while the use of matched, lossless low-pass filters allows one to vary the rise time of the incident pulse.; We analyze rigorously the breakdown process in bipolar junction transistors (BJTs), deriving general expressions for the breakdown condition of an arbitrarily configured BJT. These replace the standard expressions for open-base and common-base breakdown voltages derived in textbooks. We then apply the results of the derivation to the design of ESD protection circuits that use a vertical npn as the primary protection element.; We investigate the use of vertical thyristors in modern silicon-germanium (SiGe) BiCMOS technologies as ESD protection elements, deriving optimal design and layout guidelines for such devices. We also discuss the RF performance characteristics of SiGe thyristors compared to those of SiGe npn transistors.; We present a simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to modeling accurately the high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.