Simulation And Modeling Of ESD Protection Device On Circuit Level

The circuit-level simulation and modeling of the NMOS transistors as ESD protection devices is introduced in this paper.With the further decrease of the process feature size, the ESD problem has increasingly become a major damage factor in the chip application, and thus become a more and more important part of the chip design process. But at present, the models of the ESD protection devices used in simulation tools are not widely researched and realized. The paper is based on this background to work on the modeling of the ESD protection.On the base of depth study of the physical mechanism of the NMOS transistors used as the ESD protection devices, we first use the Hspice to simulate and analyze the present model in the condition of large current injection. And then, with the use of behavioral language Verilog-A in Cadence Spectre environment, we define and describe the circuit-level simple model of NMOS transistors, which are used as ESD protection devices. The model is composed of seven modules, every module is coded independently, representing the major physical component of the NMOS transistor under the condition of large current injection respectively. This paper also objected to certain degree of depth study of the gate-introduced drain leakage current Igidl, and then take the extraction of parameters. Ultimately, with the help of this model, we can get the characteristic curves of the NMOS transistor when be used as ESD protection devices. The modeling of the NMOS ESD devices will be a positive and practical significance for the researchful and commercial software operation.