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Performance evaluation and low power design of network processors

Posted on:2006-03-27Degree:Ph.DType:Dissertation
University:University of California, RiversideCandidate:Luo, YanFull Text:PDF
GTID:1458390008976000Subject:Computer Science
Abstract/Summary:PDF Full Text Request
As network line rate increases exponentially and new network applications and protocols are deployed, it is a challenge to accomplish both high-speed and versatile packet processing tasks in the future Internet. Network processors (NPs) have emerged as successful platforms to providing both high performance and flexibility in building powerful routers and switches. Typical NPs have optimized instruction set for packet processing and incorporate multiprocessing and multi-threading to achieve maximum parallel processing capabilities. This dissertation first studies the typical workload of an IP router and evaluates the performance of proposed shared memory multiprocessor routers for high-speed networks. To enable both performance and power consumption research of NPs, NePSim is then built as the first open source NP simulator with cycle-level accuracy and power evaluation framework. This dissertation presents the validation of NePSim and performance and power simulation results of four representative benchmark applications using NePSim. Processing Elements (PEs) are the key components responsible for processing packets in an NP. As more PEs are added onto an NP and the clock frequency of the chip increases, the power consumption of NPs has become a major concern. Two power saving techniques for NPs---Dynamic Voltage Scaling (DVS) and clock gating---are proposed. DVS exploits the idle time of PEs and dynamically adjusts the voltage and operational frequency of NPs. The experiment data shows that the power saving using DVS can reach up to 17% with only 6% reduction of the system throughput. The low power design of NP using clock gating is motivated by the observation that under low incoming traffic rates, most PEs in NPs are nearly idle and yet still consume dynamic power. Clock gating reduces the activities of PEs according to the varying traffic volume. Simulation results show that the technique brings significant reduction in power consumption (up to 30%) with no packet loss and little impact on the overall throughput.
Keywords/Search Tags:Power, Network, Performance, Low
PDF Full Text Request
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