Probe modules for wafer -level testing of gigascale chips with electrical and optical I /O interconnects

The use of optical input/output (I/O) interconnects, in addition to electrical I/Os, is a promising approach for achieving high-bandwidth, chip-to-board communications required for future generations of high-performance chips. While numerous efforts are underway to investigate the integration of optoelectronics and silicon microelectronics, virtually no work has been reported relating to testing of such chips. The objective of this research is to explore methods that enable wafer-level testing of gigascale integration (GSI) chips with electrical and optical I/O interconnects. A major challenge in achieving this is to develop probe modules which would allow high-precision, temporary interconnection of a multitude of electrical and optical I/Os, in a chip-size area, to automated test equipment (ATE). A probe module would need to do this in a rapid, step-and-repeat manner across all the chips on the wafer. The design requirements of such a probe technology have been derived. Based on these requirements, two candidate probe modules have been devised, batch-fabricated on Si using microfabrication techniques, and successfully demonstrated. The probing techniques illustrated here would find application for testing a full range of devices with electrical and optical I/Os.;The first probe module consists of vertically compliant electrical probes alongside grating-in-waveguide optical probes. The compliant probes can contact an area-array of solder bump electrical I/Os; the grating-in-waveguide probes can interface with free space, quasi-free space, or guided-wave optical I/Os. A probe substrate with 103 electrical probes/cm2 as well as grating-in-waveguide channels has been fabricated and demonstrated. The electrical probes have an average contact resistance of 0.5 Ω, and the grating-in-waveguide probes are shown to have a typical coupling coefficient, α, of 3.95 mm-1. The design is scalable to higher probe densities. The second module is micro-opto-electro-mechanical-systems (MOEMS)-based and is designed to interface polymer pillar-based electrical and optical I/Os. Each probe resembles a microsocket, and is comprised of a through-substrate via with thin-film cantilevers fabricated at the edge. Prototype probe substrates with microsocket probes at a 100 µm pitch (104 probes/cm 2) have been built. Probing of an area-array of optical and electrical polymer pillars has been demonstrated. Using a nanoindenter, the microsocket cantilever probes have been shown to survive > 160,000 mechanical cycles without any change in mechanical performance.;High-density through-wafer interconnects are an essential attribute in both probe substrates for transferring electrical and optical signals to the substrate back-side. Fabrication and characterization of metal-clad, metal-filled, and polymer-filled through-wafer interconnects as well as process integration with probe substrate fabrication is described. Numerous possible redistribution schemes are explicated.;Chips with optical and electrical I/Os are an emerging technology, and one that test engineers are likely to encounter in the near future. The contributions of this thesis are to help understand and address the issues relating to joint electrical and optical testing during manufacturing.