Low power, robust, and high performance circuit design in nano-scale CMOS

As the CMOS technology continues to scale down, power dissipation and robustness to leakage and process variations are becoming major obstacles for circuit design in the nano-scale regime. Due to increased density of transistors in a die and higher frequencies of operation, the power consumption is reaching cooling capacity limits. On the other hand, due to increased leakage and process variations, the predictability and therefore the design yield is threatened. In this research, we address theses issues mostly at the circuit level of abstraction. For the power issue, we focus on the clock power because in current high-performance microprocessors significant fraction of the total chip power is dissipated on clock networks. In this regard, we have proposed novel energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. For the leakage tolerance issues, a leakage-tolerant design technique for high fan-in dynamic logic circuits is presented that exhibits considerable improvement in leakage immunity as compared to the standard domino circuits. To address the emerging issues of process variations, we have developed yield estimation and enhancement techniques, particularly for SRAM caches. The developed yield models are used for proposing a statistical design approach for designing SRAM arrays in nanoscale regimes. Finally, novel circuit design techniques for low power and high performance using non-classical CMOS devices such as double-gate MOSFETs are developed. Particularly, independent gate operation of double-gate transistors is exploited for reducing power and/or improving performance.