A hardware implementation and analysis of the discrete cosine transform update algorithms

This work can be divided into three main objectives. The first objective is to implement hardware circuits that are capable of computing the Discrete Cosine Transform (DCT) coefficients and the Discrete Sine Transform (DST) coefficients in an efficient and optimized way (conventional mode of operation). Those circuits are built using a hybrid design that combines the butterfly flow-graph and the matrix-vector multiplication method. The hybrid design helps solving the problem of global communications that are necessary to implement the traditional butterfly flow-graph. An optimum size of 8 data points is used to implement the hybrid design. The second objective is to incorporate hardware circuits that are capable of updating both the DCT coefficients and the DST coefficients simultaneously using moving window of size 8 and step size of 1 and 4 (update mode of operation). This mode of operation aids in re-calculating the DCT and DST coefficients in their entirety (i.e., updated) based on receiving a number of data points that is smaller than the size of the window. By having both modes of operation implemented together, the capability of switching between the two modes becomes available which can be exercised in some specific cases. Finally, the third objective is to investigate the possibilities of speeding-up the architecture along with reducing the power requirements.