Hardware Realization Of The Discrete Wavelet Transform

The Wavelet Transform, as a kind of method that deal with the signal, is one of the subjects with the fastest developing speed in the past 15 years. Review the history of wavelet, we come to know that the Wavelet Transform is numerous comprehensive research results of subjects including applied mathematics, physics, computer science and engineering and so on, at the same time, it meet reality's needs, so wavelet transform must have wide prosperous future in the real life.The relations of data are complicated, the operation amount is great, calculational complexity is high in Wavelet Transform, it is hard to meet real-time requirement with software to realize Wavelet Transform, so it is necessary to realize Wavelet Transform with the hardware in order to be used in various kinds of process systems. Presently, the demand of Wavelet Transform's hardware realization become urgent following the popularization of studying and application of Wavelet Transform.By now, the research about the Wavelet Transform's hardware realization is still at the starting stage, many kinds of architecture about the Wavelet Transform is concrete, at the same time, restricted by the special Wavelet, there are many works to do to realize high-efficient and adaptive Wavelet Transform's chips which have great social value.In this article, we firstly review the history that Wavelet developed, after that, we discuss filter algorithm including FFT algorithm, Fast-running algorithm and Distributed algorithm. Afterwards, brief discussion is done about one-layer decomposition of Wavelet Transform, the emphasis in this paper is exploration on multi-layer decomposition of Wavelet Transform. In the end, Two kinds of novel VLSI implementation of Discrete Wavelet Transfrom has been presented, the former is folded architecture combined with Short-length FIR filter algorithms to reduce the number of multiplications and additions and Lifetime-analysis technique to minimize the number of registers. The later is module architecture combined with Recursive Pyramid algorithm partly.Those two architectures are suitable for different situation but all meet the demand of chip design in the speed, area , and adaptative fields.