| In this dissertation we explore the advantages of 3D integration in the context of building synthetic aperture radar image processors through two case studies. In the first case study we demonstrate a floating point FFT processor that leverages both 3D integration and a unique hypercube memory division scheme to reduce the power consumption of a 1024 point FFT down from 5.476 muJ down to 4.227muJ. In this case study the hypercube memory division scheme lowers the energy per memory access by 59.2% while only increasing the total area required by 16.8%. In the same case study, the use of 3D integration reduces the logic power by 5.2%. In the second case study we present a full SAR processor that achieves a power efficiency of 18.0 mW/GFlop through the use of a 3D memory, 3D logic-on-logic integration and datapath reconfiguration. The 3D integrated memory reduces the memory power consumption by 70% when compared to a 2D memory. The logic-on-logic 3D integration used in the PE, decreases the power consumed in the interconnect of each PE by 15.5%, the footprint of the PE by 49.2% and allows the PE to operate at a 7.1% faster clock speed. The datapath reconfiguration reduces the number of arithmetic units required in each PE from 24 down to 10. Finally, in the second case study, we explore how a 3D system can be realized using 2D tools and propose a new algorithm for TSV assignment based on Lee's algorithm. |
