Design issues and performance of large format scientific CMOS image sensors

The problems to be addressed in this dissertation are design and performance issues of large format scientific CMOS active pixel sensor (APS) image sensors. Investigation focused on four main problems of scientific CMOS APS image sensor design. They were; CMOS APS pixel development with very large pixel well-depth for high dynamic range imaging, quantum efficiency improvement in blue spectrum (400--450nm), large format image sensor design issues in where resulting die size exceeds standard CMOS manufacturing reticle size of 20mm by 20mm, and development of CMOS image sensor design and technology evaluation models and methodologies for first time silicon success.; Pixel well-depth improvement was achieved by two proposed methods; pixel photodiode peripheral utilization method (PPUM) and in-pixel capacitance use in a new CMOS hybrid photodiode-photogate (HPDPG) APS pixel. Using proposed methods, more than 4 million electrons (Me-) pixel well-depth were demonstrated in 18 mum CMOS APS pixels. Pixel quantum efficiency improvement, especially in blue spectrum (400--450nm), was achieved by improving lateral collection efficiency of photodiode type CMOS APS pixel. At least 10% quantum efficiency improvement was demonstrated at blue spectrum by placing circular openings on photodiode of CMOS APS pixels. CMOS pixel property models were developed for CMOS image sensor design and CMOS technology evaluation methodologies. A stitching CMOS image sensor design methodology was proposed for very large size image sensor design. This design methodology was demonstrated with a case study. A 16.85 Million pixel (4096 x 4114), wafer scale, CMOS APS image sensor with 1.35 million electrons (Me-) pixel well-depth was successfully designed, fabricated, and demonstrated in a 0.5 mum, 5 volt, 2P3M, CMOS process with stitching option. Pixel pitch was 18 mum. Resulted CMOS APS image sensor chip was the world's largest single die (76.08mm x 77.55mm) CMOS image sensor fabricated on a 6-inch silicon wafer until today. In addition, developed CMOS HPDPG APS pixel technology achieves largest total and unit area pixel well-depth (4Me- and 12.345 Ke-/mum2) reported in silicon based image sensors.