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Hardware accelerators for embedded speech application

Posted on:2006-03-02Degree:Eng.DType:Dissertation
University:University of Glasgow (United Kingdom)Candidate:Kirkham, AntonyFull Text:PDF
GTID:1458390008476877Subject:Computer Engineering
Abstract/Summary:
Speech technology has had, and is having, a significant impact on society. The mobile phone has created a generation of users who rely upon it to maintain their social network. Mobile phones depend upon voice compression and the Adaptive-Multi-Rate (AMR) Vocoder is the standard for GSM and G3. Automatic Speech Recognition (ASR) is waiting in the wings as the next paradigm shift in the way users interact with technology; all that is needed is robust embedded applications. Speech processing algorithms are complex, resource intensive, and therefore difficult to implement upon embedded devices. The AMR Vocoder was designed specifically for a 16bit DSP, however implementing ASR upon an embedded device remains a significant challenge. The aim of this work was to research innovative ways to implement speech applications to either reduce the required resources or significantly increase application capabilities. The achievements are: A novel hardware accelerator was designed for the AMR Algebraic Codebook Search which reduced the power consumption by a factor of 5, thereby potentially increasing the battery life of a mobile device. A novel hardware accelerator was developed to speed up the calculation of Observation Probabilities during ASR, which leads to increased robustness and larger vocabularies in embedded devices. A novel hardware accelerator was developed to achieve Speaker Adaptation for a Hidden Markov Model in approximately 4.6 seconds on an embedded device. This is near workstation performance, and has the potential to revolutionise embedded ASR applications.
Keywords/Search Tags:Embedded, Speech, Hardware accelerator, ASR
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