Hardened by design approaches for mitigating transient faults in memory-based systems

In radioactive environments, particle strikes can induce transient errors in integrated circuits (ICs). Strikes directly disrupting memory are known as Single-Event Upsets (SEUs), while strikes initially disrupting logic are called Single-Event Transients (SETs). Chips manufactured in aggressive technologies may also experience Multiple-Bit Upsets (MBUs). This research focuses on novel hardened by design circuit-level approaches to protecting integrated circuits against SEUs, SETs and MBUs. A number of system-level designs have been developed utilizing these approaches to demonstrate their capabilities.; Many of the design-hardened memory circuits considered in this study share a common theme, which is the ability to bypass transient faults. This is critical for performance, as it allows a system to proceed with subsequent operations while recovering from a disruption. Among the considered approaches, the novel Triple Path DICE (TPDICE) structure is the most balanced. This structure requires only two of its three inputs to be resolved during a write operation to ensure recovery. The recovery process requires approximately 50-100ps in 0.18mum CMOS.; A number of digital system applications for these approaches have been designed as part of this research. These applications include an SET-tolerant reconfigurable digital signal processing (DSP) architecture, SET-tolerant pipeline memory circuits, and an MBU-tolerant memory design. The radiation-tolerant DSP architecture is a memory-based system relying on TPDICE circuits to provide fault tolerance. Redundancy and additional circuit-level techniques are adopted to improve system-level reliability.; SET-tolerant pipeline memory structures are introduced to provide a means for protecting computational datapaths against faults. A number of single-ended and differential structures are presented and evaluated with respect to performance, energy consumption, and timing. Latches, master-slave flip-flops, and pulse-triggered flip-flops each offer a distinct balance of these comparison attributes.; Finally, a novel MBU-tolerant design is depicted, which utilizes layout-based interleaving and multiple-node disruption tolerant memory latches. This approach protects against non-grazing as well as grazing incidence particle strikes. Advantages with respect to size, complexity, and MBU tolerance are realized when compared to existing solutions.