| Flash and other non-volatile memories can have faults that can not be modeled by traditional fault models. Disturb faults are a class of such faults caused by defects within the insulating layer of the memory transistor. There are three types of disturb faults namely, DC-program, DC-erase, and drain disturb. In this thesis, fault models based on single and multiple defects in the memory cell are developed and faulty cell behavior under each model is described. Optimal and near optimal tests that detect different disturb faults are developed and analyzed. Using data from a device simulator, an electrical model (SPICE model) for a 1T flash bitcell is developed. A technique to inject defects in the model is developed and faulty cell behavior is simulated. Manifestation of the different faults at logic level is validated using SPICE model simulation and the efficiency of the different tests and their defect coverage are analyzed and discussed. |
