A multiprocessor array architecture for DSP and wireless applications and case study of an IEEE 802.11a receiver implementation

Multimedia processing and wireless communication are increasingly gaining attention in both academia and industry aiming at the design of low-power, high-performance, and flexible solutions to efficiently handle complex tasks in real-time and in a cost-effective manner. Currently, with different standards delivering different services for instance WLAN [1], WPAN [2], WMAN [3], CDMA based cellular networks and their high speed extensions [4], DVB-H [5-7] the importance of programmability is highlighted as convergence of devices is the industry trend.; In this research, we investigate two-dimensional multiprocessor array architectures targeting Multimedia and wireless applications. Having the experience of the MorphoSys project [8-12] and being aware of its shortcomings and strengths, we propose MaRS, a Macro-pipeline Reconfigurable System [13-14]. As an example of a high-rate complicated application, we used the physical layer of IEEE 802.11a [15] Wireless LAN standard throughout the design process as an example of application-platform co-design. As a part of this research, a fully compliant IEEE 802.11a simulator is implemented using Matlab leading to a set of VLSI suitable synchronization algorithms [16] and a novel soft decision Viterbi decoder incorporating channel state information [17].; In order to further evaluate the performance of MaRS, the communication suit of EEMBC benchmarks [18] are investigated along with some future applications. It is noticed that forward error correction coding, is the killer application; therefore, popular FEC coding algorithms including different types of convolutional codes, and Reed Solomon codes are studied in details and the proposed modification to architecture and ISA are proposed along with the analytic evaluation of their computation cost.; The organization of the dissertation is as follows. In the introduction, the previous work, background and motivation for this work are presented. Then the MaRS architecture is elaborated in details. Chapter three explains the programming model of MaRS with some examples of parallel mapping on the architecture and presents some parallel application benchmark comparison. An overview of the IEEE 802.11a model and proposed algorithms are presented in next Chapter along with the algorithms mapping in a pipeline fashion on a 10x10 array of processing elements in MaRS. Chapter 5 treats the mapping of Reed Solomon decoder on MaRS array. Chapter 6 is dedicated to the study of parameterizable Viterbi decoder on MaRS. Future works and conclusions are presented in the final Chapter.