Advanced gate technologies for deep-submicron CMOSFETs

The scaling of CMOSFETs into the deep-submicron regime necessitates the introduction of advanced gate technologies. In the near-term (≥32 nm technology nodes), poly-crystalline silicon (poly-Si) will continued to be used as the gate material, but requires the introduction of novel gate annealing techniques. This is because Rapid Thermal Annealed (RTA) poly-Si gate electrodes usually show either the gate depletion effect or boron penetration through the gate dielectric.; Pulsed Excimer Laser Annealing (ELA) is proposed as a near-term solution to the gate stack challenges. By using ELA, an amorphous Si gate electrode can be completely melted so that the implanted dopants diffuse rapidly (D =∼ 10-4cm2 /s) to the interface and are activated upon Si crystallization. It is found that effective active dopant concentration >3 x 10 20cm-3 can be attained for both nMOSFETs and pMOSFETs, so that the gate depletion effect is reduced to ∼0.1mm Equivalent Oxide Thickness (EOT). It is also found that, although the gate electrode is heated to very high temperature (>1200°C), the process time is sufficiently short (∼100ns) so that the underlying gate dielectric (SiO2) is not damaged and there is no dopant penetration. The ELA technique is also compatible with H fO2 gate dielectric, and ELA PMOS capacitors have 5-7 orders of magnitude lower leakage current density than the RTA control samples.; After ELA, the effective Work Function (WF) of a p+ poly-Si gate is reduced by ∼470meV. This is probably due to generation of vacancies and interstitials during the quenching process, resulting in Fermi-level pinning. However, the WF can be recovered by furnace annealing at moderate temperature.; In order to incorporate melt-ELA technique into a conventional CMOS process, we have proposed, studied and demonstrated two possible integration schemes (Selective ELA via Masking and ELA Self-Aligned STI process).; In the long term (<32nm technology nodes), novel transistor structures (e.g. thin-body MOSFETs) will require metallic gate materials with tunable WF to eliminate the gate depletion effect and to adjust transistor threshold voltage. Fully-silicided (FUSI) Nickel Silicide is one of the most promising candidates. In FUSI technology, nickel is deposited onto a poly-Si gate to form a fully silicided film, and the WF is tuned by incorporating impurities (e.g. B, P) by ion implantation before metal deposition.; We show that the WF of impurity incorporated FUSI NiSi gate is adjustable between ∼4.5eV and ∼4.9eV. By using the pulsed excimer laser as an experimental tool, it is found that both dopant activation and initial dopant distribution are critical in the WF tuning. Gate oxide qualities (leakage current, TZDB, QBD) of boron doped FUSI gate are found to be better than those of p+ poly-Si reference in pMOSFETs, while those of phosphorus and undoped FUSI gate are comparable with those of n+ poly-Si reference in nMOSFETs. It is also found that doped FUSI gates have better thermal stability to withstand backend process annealing.