Fabrication And Characterization Of Ni-Based Fully Silicided Metal Gate

The tunneling current through SiO₂ or SiON increases exponentially as the dimension of complementary metal-oxide-semiconductor(CMOS) devices is scaling. As a result,SiO₂ or SiON should be replaced by high-k gate dielectric.However,the conventional poly-Si gate has many problems,such as poly-Si depletion effects,and the imcompatibility with high-k dielectrics:Fermi-level pinning and charge-carrier-induced mobility degradation.Poly-Si gate must be replaced by metal gate with higher conductance.Fully silicided(FUSI) metal gate has been investigated extensively due to its large work function(WF) modulation range and excellent compatibility with the conventional CMOS field effect transistor process.This paper investigates the fabrication process,electric performance,WF modulation,SiO₂/Si interface trap properties,and electrical characterization of FUSI metal gated MOS capacitor.Capacitance-voltage(C-V) measurement principle and analysis.By investigating the effects of measurement frequency and capacitor area on C-V measurement results, three or four element equivalent circuit model must be used,when the oxide leakage current is large(for example,in ultra thin gate oxide).The reduction of capacitor area can decrease dissipation factor D and therefore obtain reliable C-V characteristic curves.Pre-doping effects on Ni FUSI metal gate.First,the thesis investigated the fabrication process and characteristics of Ni FUSI metal gate formed from solid reaction of a-Si and Ni by sputtering on three different SiO₂ thickness.The WF of the FUSI metal gate is 4.40 eV.Then,the thesis investigated the effects of ion implantation and spike activation anneal on the WF modulation of pre-doped Ni FUSI metal gate electrodes on SiO₂ dielectrics,and the FUSI gated SiO₂/Si(100) interface trap properties.The interface trap properties were measured by using high-frequency C-V and photonic high-frequency C-V measurements.After fully silicidation anneal, the flatband voltage(V_FB) of the Ni FUSI gated MOS capacitor shifts negatively or positively for As-doped or B-doped case,respectively.As-doped Ni FUSI gate may delaminate or peel off after forming gas anneal(FGA).Undoped NiSi FUSI gate has good thermal stability,and its WF before and after FGA is 4.75 eV and 4.74 eV, respectively.Interface trap density D_it calculated from the photonic high-frequency C-V curves is in good agreement with that calculated from the high-frequency and photonic high-frequency C-V curves.Before FGA,a characteristic D_it peak ranging from 5.7×10¹² to 1.2×10¹³ cm^-2eV^-1 was observed at approximately 0.63～0.74 eV above the valence band edge for As-doped and B-doped Ni FUSI gated capacitors which received a spike activation anneal after ion implantation._The characteristic peak,which may be related to P_b defects at the SiO₂/Si(100) interface,could be eliminated after FGA.Ni(RE) FUSI metal gate.The thesis investigated the rare-earth(RE) metal alloying effects on the sheet resistance,the WF modulation of Ni(RE) FUSI gate electrodes.As the thickness percentage of Ho in the Ni(Ho) increases from 0 to 13%and 30%,the sheet resistance of the silicide increases from 1.4Ω/sq to 1.8Ω/sq and 3.1Ω/sq,and the V_FB shift decreases from -0.31 to -0.50 and -0.58 V.The V_FB shift can be attributed to the WF decrease due to Ho.As the thickness percentage of Er in the Ni(Er) increases from 0 to 10%and 32%,the sheet resistance of the silicide increases from 1.4Ω/sq to 2.1Ω/sq and 4.9Ω/sq.The WF is reduced approximately 0.17 eV due to the 10%Er thickness percentage in the Ni(Er).