Optimization Of Ⅲ-Ⅴ MOS Devices Interface And Fabrication Process

Since the Si-based transistors are approaching their fundamental limits, Ⅲ-Ⅴ compound semiconductor materials have been actively investigated for their advantages over Si-based counterparts in carrier mobility and injection velocity. A high quality dielectric/III-V compound semiconductor gate stack structure, low resistivity source/drain and good electrical properties of MOSFET are necessary. In this paper, GaSb based MOSCAP interface passivation, GaSb and InGaSb based MOSFETs fabrication, ion implanted GaAs and its ohmic contact, InGaAs channel MOSFETs fabrication is studied. The main research contents of this dissertation are as follows:(1) Optimization of the interface of GaSb based MOS devices. The influence of two postgate treatment processes, including post metallization annealing (PMA) and CF4 plasma treatment, is demonstrated on atomic layer deposited (ALD)-Al2O3/n-GaSb gate stack. Through a combination of CF4 plasma treatment and PMA in N2 ambient, the border trap density and interface state density (Dit) have been decreased by 15.8% and 47.5%, respectively. X-ray photoelectron spectroscopy (XPS) analysis shows clear evidence for the formation of Al-F-O and Al-F bonds by the CF4 plasma treatment. It is suggested that PMA in N2 ambient and postgate CF4 plasma treatment can be used to effectively passivate the interface and bulk oxide traps that create improvement in electrical characterization.(2) Sb-based pMOSFETs fabrication. Mg-implanted source and drain GaSb pMOSFETs were fabricated by the gate-last process. For a 2 um gate length GaSb pMOSFET, a maximum drain current of about 11.5mA/mm and the Ion/Ioff of over 3000 have been achieved. An InGaSb buried-channel pMOSFET has been fabricated by using digital etch technique for active area definition and gate recess etching. The exposed n+ InAs cap was etched by UV ozone exposure and dilute HCl dip. For a 1 um gate length InGaSb buried-channel pMOSFET, a maximum drain current of about 26.1 mA/mm, a peak transconductance of 9.9 mS/mm, an Ion/Ioff of about 80, and a SS of about 330 mV/decade have been achieved.(3) Ion implantation and ohmic contacts for semi-insulating GaAs. The temperature and time conditions for Mg ion-implantation and annealing are optimized. It was found that, when the activation temperature is too low, the activation is not sufficient, and then the sheet resistance will be large. On the other hand, when the temperature is too high, it will damage the materials and devices. We found the best annealing temperature for Mg ion-implantation was 800℃ and the best anneling time was 10 sec, while the best anneling temperature for Zn ion-implantation was 650℃.(4) InGaAs channel MOSFETs fabrication. Be-implanted source and drain InGaAs pMOSFETs were fabricated and the devices exhibit decent electrical properties. Finally, a new nMOSFETs structure was proposed based on the same epitaxial structure.