Silicon-germanium based negative differential resistance memory and lattice-mismatched film growth

The increasing speed gap between the logic and DRAM technologies has led to complex memory hierarchies and the need for very large quantities of high speed on-chip memory. While maintaining a significant density advantage, traditional DRAM devices have suffered from poor performance compared to SRAMs. As technology develops, DRAM design is increasingly constrained by data retention problems. For example, high speed operation requires reduced threshold voltage of the access transistor, resulting in an exponential increase in subthreshold leakage and therefore worse data retention time. One possible solution to the above problem is to add negative differential resistance (NDR) elements to 1T1C DRAM cells to form bistable circuits. If the current of the NDR element is high enough to compensate for the cell leakage, the information stored in the capacitor will not be lost and a static high-density memory cell can be achieved. However, conventional NDR devices showed low peak-to-valley current ratios and involved either CMOS-incompatible processes or very large cell areas.; This work presents a novel CMOS-compatible NDR device based on SiGe gated tunneling diodes. SiGe/Si heterostructure allows us to optimize the peak and valley current independently: the peak current is dominated by the tunneling currents which can be enhanced by the SiGe film whereas the valley current comes from bulk generation which can be suppressed by the Si substrate.; Four{09}configurations were proposed to convert the gated{09}diode to NDR devices. The transistor-buffered SiGe NDR device received most interest because of its excellent controllability and process simplicity. The fabricated SiGe NDR devices demonstrated large peak currents and high peak-to-valley current ratios (PVCR). Without further optimization, the PVCR of this device has already reached 300 at room temperature which is probably the highest reported PVCR in Si compatible systems to our knowledge. Our NDR device presents excellent scalability and can be easily integrated into a DRAM cell with a small area penalty. It is a very promising candidate for embedded memory applications, combining the advantages of both SRAMs and DRAMs---more compact than SRAM cells and unlike DRAMS no need for' refreshing, ultimately enabling higher speed operation with lower power.