Supporting Both Superpage And Large-Capacity DRAM Cahce In Hierarchical Hybrid Memory System

The popularity of big data applications requires large capacity of main memory.Traditional Dynamic Random Access Memory(DRAM)can not meet this requirement duo to the limited memory density and high power consumption.Emerging Non-Volatile Memory(NVM)such as Phase Change Memory(PCM)has higher storage density and near-zero static power consumption,at the expense of limited write endurance and lower performance.It is more practical to construct large-capacity hybrid memory together with DRAM and NVM.Big data applications usually suffer large performance overhead duo to high TLB miss rate.Using large pages can significantly increase TLB coverage and effectively reduce TLB miss rate.However,large pages often precludes lightweight memory management such as page migration because the large gratitude of page size can lead to high overhead in terms of memory bandwidth and energy consumption.In this paper,we propose a hybrid memory management strategy supporting both large page and large capacity DRAM cache.Hierarchical hybrid memory architectures do not have the difficulty of migrating fine-grained hot data within large pages into DRAM cache.We propose to use direct mapping between DRAM and NVM while using 4KB large-grained data blocks in the DRAM cache.Therefore,our strategy can support big capacity DRAM cache by shrinking the metadata size to fit into the on-chip cache.In order to prevent the frequent data fetched from NVM to DRAM,we proposed a filtering mechanism to reduce the fetch operation upon DRAM cache misses to alleviate bandwidth pressure.Only hot data that exceeds the threshold can be cached in DRAM.A dynamic threshold adjustment strategy based on memory real-time access information has also been proposed to adapt the changes of memory access pattern.Experiments show that our strategy has an average performance improvement of 69.9% and 15.2%,respectively,compared to pure NVM memory using large pages and a state-of-the-art strategy,and the performance is only 8.8% lower than a full DRAM memory system using large pages.