Silicon nanocrystal devices for electronics and photonics

This work explores the application of two different types of nanocrystalline silicon (nc-Si) structures to meet the challenges facing CMOS VLSI. In the first part, the fabrication and properties of nc-Si and Ge embedded in SiO 2 and Si3N4 is investigated for application to an optical interconnect layer over CMOS devices. The main focus is on co-sputtered layers from Si and SiO2 targets although implanted and CVD matrixes of Si3N4 are also presented. The characterization tools include: photoluminescence (PL), XPS, spectroscopic ellipsometry, TEM and ESR spectroscopy. Dangling bond termination by either forming gas annealing or high pressure water vapor annealing (HWA) is critical to obtaining high efficiency PL emission. This study reveals the PL enhancement mechanism of nc-Si by HWA. The dependence of the PL intensity and the peak shift on the different nanocrystal materials studied suggests the differences in the emission mechanisms. The band-to-band direct recombination dominates in nc-Si in SiO 2, while emissive states are the PL source for the Si3N 4 matrices. The results indicate that these materials should be useful for electroluminescence emission devices in the 700-800 Mn wavelength range for high speed optical interconnect applications in CMOS.; In the second part, a novel device layer transfer technology based on nanocrystalline porous silicon is proposed. This technology is applicable to 3D device layering and to optical interconnect layers on the existing device layers. A bulk wafer is anodically etched to make porous silicon, followed by silicon epitaxial growth on the porous silicon. Conventional CMOS devices are fabricated on this epitaxial layer. In the final step, the device layer is transferred to a plastic substrate with grinding as the thinning process. We found that the CMOS characteristics with a porous silicon underlayer are comparable with those without the porous silicon. We also demonstrate that no degradation of the CMOS electrical characteristics occurs during transfer, suggesting that the porous silicon transfer is suitable for fabricating 3D-ICs and flexible ICs and for enhanced die cooling for high performance processors.