| Ultrathin body MOSFETs are suitable in sub-50nm technologies due to their excellent immunity to short-channel-effects and increased radiation hardness. However, at extremely scaled gate lengths (< 20nm), these devices pose some serious challenges such as increased drain-induced-barrier-lowering (DIBL), exponentially higher leakage, dominating parasitic capacitances and large process variations. We propose device optimization techniques for multiple-gate FETs to reduce power dissipation and improve robustness in logic and memories. We optimize the transistor channel length by varying the gate sidewall offset spacer thickness instead of varying the printed gate length. Our proposed technique reduces short-channel-effect and off-state sub-threshold and gate edge leakages. To analyze the short-channel-effect dependence on device geometry, we model the body potential distribution in a double-gate FET in sub-threshold region. Increasing spacer thickness also reduces gate to source/drain extension overlap and fringe parasitic capacitances resulting in reduced dynamic power dissipation. We developed a compact analytical model to compute the gate sidewall fringe capacitance which we further employed to compute the capacitances between the non-overlapping interconnects in different layers. We optimized the multiple-gate FETs to design low-power and robust SRAMs. We explored the design optimization window for reducing cell leakage and improve read failure probability with minimal effect on write margin, data retention voltage and access time. Further, we propose a dual-threshold voltage methodology to reduce leakage power dissipation in high-performance circuits. |
