A methodology for the hardware/software co-design of embedded systems

The design of hardware and software for embedded systems is well understood. But the compatibility problems between the two parts increases the time and effort of exploring the system design space. This research lies at the interface between hardware and software design to reduce incompatibilities. This research has contributions in hardware verification and automatically retargetable software.; This research is unique because the microarchitecture of the embedded system is an input to the methodology rather than a fixed structure. The semantics of the instruction set architecture are described as an ISA extension language added to the architectural description. The extensions are considered assertions, are verified in the microprocessor hardware and are constraints in the automatic retargeting of software.; The architectural verification portion of this research considers both the structure and timing of data and control in the microprocessor datapath. A technique named structural correctness verifies the structure of the datapath has the required number and types of operand paths, execution units and control signals. Structural correctness is based on a path searching technique. Another technique named Hardware Token Graph (HTG) semantic model and simulation rules verifies the timing synchronization of data and control. The microprocessor states represent the location of data and control passing through the datapath at clock edges. The semantic model is analyzed using a simulation reachability analysis. The generated reachability tree is examined for the desired states which correspond to the correct operation of the microprocessor.; The software portion of this research describes an automatically retargetable optimizing assembler. A novel technique for software optimizations performs integrated instruction scheduling and register allocation under resource-conflict and data-dependency constraints. The software instruction scheduling is based on a priority schedule technique, and the register allocation is based on a linear scan allocation.; An implementation of this methodology has been developed named RAVE (Retargetable optimizing Assembler with architectural VErification). RAVE has been applied to instruction set trade-off analysis for edge detection and DNA sequencing applications to demonstrate its utility with promising results.