| This research has produced a new methodology called ISAS (Instruction Set Architecture Assessment System) for performance assessment of proposed and existing instruction set architectures, independent of implementation and realization technologies. The methodology supports the configuration of one, two and three-address, scalar SISD (Single Instruction Single Data stream) architectures with a wide array of operation sets, operand access and addressing modes, register set architectures and subroutine linkage mechanisms. After menu-based selection of desired architectural elements from an ISA taxonomy, a compiler, an assembler and a virtual machine module, using a standard mnemonic set for the target architecture, are automatically configured. C benchmarks, representing the target environment, can subsequently be compiled, assembled and virtually executed to generate a variety of architectural performance measures, including bit budget, bit traffic and number of static/dynamic instructions. The methodology has been validated by comparing measured data from two existing architectures with data obtained by modeling these architectures directly in ISAS. A comprehensive series of architectural case studies modeled in ISAS additionally demonstrate the applicability and practicality of the methodology in performing efficient architectural assessments. |
