| Power has become one of the primary design constraints in modern embedded microprocessors. Many embedded applications perform computationally demanding tasks, such as signal processing and encryption, that require high performance processors. Hence, traditional power savings techniques that sacrifice performance for power are not always applicable. It is well known that the memory sub-system is responsible for a significant fraction of the overall power dissipation. On-chip memory structures, such as register files, caches, and scratch-pads, provide fast and energy efficient access to program and data by reducing the slower and power hungry off-chip accesses. Memory power, therefore, can be reduced by employing techniques to effectively utilize these storage elements. In this dissertation, three different compiler orchestrated, but hardware-assisted techniques, are proposed that target these on-chip storage elements while remaining performance neutral.; A windowed register file architecture that provides a large number of physical registers without compromising on the instruction encoding is proposed. A novel graph partitioning compiler algorithm was designed that partitions virtual registers within a procedure across multiple windows. This reduces memory demand by avoiding spills, thus improving both power and performance.; Scratch-pad memories, unlike traditional hardware caches, lack the complex tag checking and comparison logic, thereby proving to be efficient in area and power. A compiler managed dynamic instruction placement algorithm was designed wherein, multiple hot code sequences are made to overlap each other in the scratch-pad at different points in time during execution through specially provided copy instructions.; Finally, data caches have been effective in dealing with more irregular data access patterns. But, they employ hardware-based lookup and replacement schemes that have high energy overheads. A partitioned data cache architecture is proposed in which, enhanced load/store instructions are used to control fine-grain data placement and lookup within a set of cache partitions. This fine-grain control can avoid conflicts, thus providing the performance benefits of highly associative caches, while saving energy by eliminating redundant tag- and data-array accesses.; These techniques are evaluated within the context of a low-power WIMS microprocessor resulting in a combined system energy savings of around 32%. |
