High performance crossbar switch design

According to the International Technology Roadmap for semiconductors, within the next decade, System-on-Chip (SoC) design will grow to 4-billion transistors running at frequencies in excess of 10 GHz. The greatest challenge facing the successful utilization of these systems is the design of reliable, functional, scalable and power efficient communication between the individual components. This new challenge has created a "Network-on-Chip" design paradigm.; The on-chip networks of future complex SoCs will have stringent bandwidth and latency constraints as well as reliability requirements that are similar to that of interconnection networks for current high-performance multi-processor systems. To achieve the interconnect performance requirements of future multibillion transistors SoCs, the interconnection network (physical interconnect and switches) must support multi-GB/s link bandwidths, and stringent latency requirements in an area and power efficient manner.; This work addresses address the issues related to improving the performance of future on-chip networks. This dissertation proposes migration from conventional static CMOS to reduced-swing current mode switching within the crossbar switch and interface between crossbar switches to improve the bandwidth and power efficiency of on-chip interconnection network. Anew current-switched logic style called low-swing split-drive pass-transistor logic (LSST-PTL) is proposed as an alternative to static CMOS logic.; In order to exploit the power benefits of reduced-swing current-mode data transmission, the data must be received in a power and area efficient manner. This requires the development of area efficient, high-sensitivity, high-speed and low-power data receivers and the development of low power all active broadband amplifiers for low-skew low-jitter on-chip clock distribution at multi-GHz clock frequencies. An innovative sense-amplifier and a sense-amplifier flip-flop that can be used as power and area efficient high-speed data receivers, within crossbar switch and external interface, is proposed to receive and retime the reduced voltage swing signals.; The use of proposed crossbar architecture, which incorporates current switching, and an innovative SA for swing restoration, and all-active differential amplifiers for intra-element clock distribution, can significantly improve the bandwidth, bandwidth density and power efficiency of future on-chip interconnects.