Energy-efficient and error-tolerant digital design

Aggressive technology scaling and design practices have increased the impact of noise in high-performance digital systems. Nanometer CMOS process technologies in the sub-45-nm regime have become statistical in nature. In this dissertation, we study the problem of designing deterministic systems even though the constituent blocks exhibit statistical behavior. We study the energy-efficiency versus reliability trade-offs in the context of digital signal processing and communications systems.;Recently, communications-inspired techniques of error detection and error correction using algorithmic noise-tolerance (ANT) have shown enormous promise in jointly optimizing energy-efficiency and robustness of nanometer systems-on-a-chip (SOCs). We introduce a novel ANT technique referred to as Input Subsampled Replica (ISR) ANT which can be applied to motion estimation block in a video encoder. The motion estimation block is the most power hungry block in a video encoder. The proposed architecture employs the principle of error-resiliency to combat logic level timing errors that may arise in average-case designs in presence of process variations and/or due to overscaling of the supply voltage (VOS) and thereby achieves power reduction. Error-resiliency is incorporated via ISR-ANT where an input subsampled replica of the main sum-of-absolute-difference (MSAD) block is employed for detecting and correcting errors in the MSAD block.;Next, we extend the communications-inspired approach by proposing the use of networked computational units that compute and communicate with each other in order to provide robustness and energy-efficiency. Referred to as stochastic sensor network-on-a-chip (SSNOC), this novel design paradigm seeks to embrace randomness and non-determinism in circuit fabrics as opposed to treating the latter as sources of errors that need to be corrected. In the SSNOC paradigm, computation is viewed as distributed estimation problem and robust estimation theory is employed to achieve robustness and energy-efficiency in presence of nanoscale non-idealities such as process, temperature and voltage variations as well as soft-errors due to particle hits. The utility of the proposed framework is demonstrated by employing it to design an energy-efficient and robust PN-code acquisition system for the wireless CDMA2000 standard. Emulation using Altera field programmable gate array (FPGA) board verifies the robustness of SSNOC-based PN-code acquisition for 430 different error statistics with probability of sensor error lying between 4% and 60%.;Thus, our proposed techniques address the challenging problem of energy reduction and reliable operation in a unified manner. They enable us to design deterministic systems even though the process technology has statistical variations. These techniques provide a new computational model that is better suited to the realities of the nanoscale era. Such computational models may be key to extending Moore's law into the deep nanoscale silicon and post-silicon era.