A Research On Some Key Techniques In The Digital Channel Simulator

Based on the analysis of the characters, the current status and developing trend of digital channel, this paper gives an idea of setting up a digital channel simulator (DCS) flat. The research includes: study the characters of digital channel, converse all kinds of communication interface standards, handle DSP techniques and use CPLD. Altogether, the paper contains four major parts:In part one, the character of digital channel is discussed, especially analyse and research the index of error bit, jetter and wander in digital transmission impairment. Bring forward a way of channel simulator: simulate the baseband digital channel. At the same time, construe some main parameters and performance.In part two the simulative arithmetices of error bit, jetter and wander are advanced. Based on the trend of digital communication development, adjusting someperformance such as error bit rate (BER) to 10-10, which is 10-6 as a rule. In thisway, we can get a DCS which has wider range and higher precision. To realize the jetter and wander, comparing with two theories of realization and selecting the circuit realization which is simpler comparatively. Through the uniform sampling method can produce the sine wave, which is more approachable the standard sine wave.In part three the design and realization of digital channel simulator is introduced. The purpose of this section is to construct a hardware flat, which has favorable compatibility and expansibility to realize the essential function. For about hardware design, DSP technique is chosen because of its super operating ability and powerful I/O access ability. Through the CPLD that can in system programme to desing the jetter and wander bring the advantage of concision and agility. This means make the system achieve the target of more small, intelligentize and universal, convenient for the extension and upgrade for the future.In part four the problem of how to realize the interface of the digital channel simulator is figured out. It includes the serial interface circuit and UART. Aiming at the request of multi-protocol serial interface, instead of pile up some serial interface chips, the author choose the SP507 multi-protocol serial interface chip as the system's interface chip. The circuit can support manifold complicated physical layer protocol and is more flexible, convenient and simpler. To design the G.703 interface circuit, make use of the characters that the DSP chip supports the T1/E1 protocol masterly, connect the G.703 interface chip to the DSP chip directly. And another peculiarity ofsystem is the design of UART, which is completed by CPLD. The virtue of this wayi is settled other UART chip's disadvantages such as low transmit rate and complicated performance. On the other hand it can achieve some especial requests such as the choice of data format. Thereby improve the utilization and reduce the resource of system.