From synchronous to GALS, the architecture of FPGA

The conflictual demand of faster and larger designs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a Globally Asynchronous Locally Synchronous (GALS) one. Such changes imply more synchronization constraints, but also more flexibility.;To achieve better performances, a novel FPGA architecture that is compatible with existing devices and that can support GALS designs natively is presented. The main objective is simple: the proposed architecture must appear unchanged for synchronous design, but also includes a minimal amount of basic components to prevent metastability for efficient asynchronous communications. A pausible clock generator application and simulation results for the proposed architecture is presented. All results demonstrate that with a few additional customized circuits, a standard FPGA cell can become appropriate for GALS methodologies.;A glitch masking circuitry is finally presented to mask completely metastability and avoid synchronisation problems. The aim is to define a circuit able to implement physically the constraints that mask metastability sources and that appear transparent during synchronization. Simulation results confirm that such a circuit can totally mask metastability sources with no performances degradations, introducing only a latency equivalent to the setup time of a typical flip flop.;Keywords: GALS FPGA, components, architecture, glitch masking.;Consequently, a methodology for implementing GALS design in conventional FPGAs using existing tools is first presented. The goals are to define the minimal set of basic asynchronous components, to permit the methodology of their implementation and to establish the design constraints and limitations of such circuits. Simulation results confirm that GALS designs implemented using the Look-Up Table or the Flip-Flop with Place & Route tools and asynchronous components such as the delay element, the Muller-C element or the arbiter are supported by conventional synchronous FPGAs as long as these designs are implemented within suitable constraints and operated within well defined circuit limitations.