| The demand for richer services, multifunctional portable devices and high data rates can be only envisioned due to the improvements in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling - increased power dissipation and parametric variations. The contradictory design requirements of these issues makes the development of low power and robust systems one of the most challenging design problem today. To that effect, we present cross-layer methodologies that address low power and variation-tolerance with low-overhead, at the system level where it is possible to effectively trade-off circuit level metrics such as power and delay with system level metrics such as quality-of-results and tolerance-to-variations. The proposed techniques exploit algorithmic properties to modify the computational complexity of digital signal processing systems in order to tackle delay failures, the common symptoms of parametric variations and voltage over-scaling, which is very effective in power reduction. The principal idea is to protect the significant computations of an algorithm that contribute significantly to the output quality by combining circuit/architecture techniques ensuring that any delay failure will affect only the less contributive computations, thereby leading to minor/acceptable quality degradation. The proposed significance driven design technique is applied to various types of designs that include logic and memory architectures and digital-signal-processing systems. Specifically, the technique is adopted to the design of ubiquitous logic blocks of DSP systems, FIR filters, color interpolation and discrete cosine transform architectures. Furthermore, a novel low power and robust embedded memory for multimedia applications is developed by combining the significance driven approach with circuit and architecture level memory design techniques. Finally, HERQULES, a unique and elegant mathematical solution to the exploration and identification of energy efficient techniques at the various levels of hardware stack that takes into consideration system level interactions between the blocks of a system is presented. |
