Design techniques towards a full-rate 40Gb/s transmitter in 0.18mum CMOS

We investigate high-speed design techniques that enable realization of a full-rate broadband serializer operating at 40Gb/s using a 0.18mum CMOS process. Bandwidth enhancement techniques, including shunt-peaking and multi-pole bandwidth enhancement, have been incorporated in the different high speed blocks in the serializer. Different inductor structures have been studied and appropriately incorporated for bandwidth enhancement and resonating circuits, consistent with various constraints on speed, quality factor, and chip area. A novel dynamic re-timing circuit capable of clocked 40GHz operation is presented, which reduces the duty-cycle distortion at the serial output. A low-power distributed buffer with unequal characteristic impedances in the gate line and drain line is designed as a 40Gb/s output buffer. A method for generating a differential 40GHz clock using two coupled 20GHz oscillators with a "push-push" topology is also proposed. Harmonic distortion and phase noise of a 40GHz push-push VCO with appropriate buffering of the 20GHz and 40GHz clock signals are studied. An injection-locked divider based on a four-stage ring oscillator with two injection point has been designed for generating a 10GHz clock signal. Use of fully differential dividers, phase frequency detector (PFD) and charge-pump which have been designed to realize a clock multiplying unit (CMU), have been studied.