| The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations.;In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius. |
