Electrical characterization of silicon-on-insulator wafers

Silicon-on-Insulator (SOI) metal oxide semiconductor field effect transistors (MOSFET) have become a common subject in the semiconductor community due to enhanced performance such as simple processing, excellent scalability, sharp subthreshold characteristics, minimum short-channel effects, and reduced hot electron degradation. Since these films are used for devices, it is necessary to know the SOI film quality with simple and nondestructive methods. In this study, surface photovoltage (SPV) measurements, pseudo-MOSFET characterization, and capacitance-voltage (C-V) are used. Literature review and simulations show that material properties of SOI wafers can have significant effects on the device and circuit performance such as floating body effects, switching speed, leakage current, and noise characteristics. SPV results show the surface charges of SOI wafers to increase with frequency in the low frequency region, with several interface components acting in opposing directions.{09}Iron contaminated wafers show increased surface charges due to a high density of interface states. The efficacy of surface passivation is clearly shown by measuring the effective generation lifetime as a function of time after applying the liquid to the pseudo-MOSFET surface. A more controlled method is the additional top gate controlling either the upper or lower silicon film surface, separately. C-V measurements for some SOI wafers show a leaky buried oxide (BOX) and high density of interface states. SOI wafers can exhibit quite different breakdown voltage before and after removing the Si layer, indicating that the gate current flows through weaker current paths in the BOX beyond the gate area. Transmission electron microscopy (TEM) images display smooth interfaces and a clean BOX, regardless of the breakdown voltage.