Study Of Reset Failure Phenomenon In Cation-based Resistive Switching Devices

Scaling down with Moore's Law is the main approach to improve the density of the integrated circuit in the past few decades.At present,the semiconductor feature size has been developed to the 14nm technology node,and chanlleges resulting from the device intrinsic physical mechanism makes it increasingly difficult to develop forward.Cation-based resistive switching device,which is an emerging nano-information devcie relay on new principles,new materials and new structures,has shown promising potential in non-volatile memory,logic circuit and neuromorphic computing due to the superior re-sistive switching performances.It is an important candidate to fulfill the demand of next-generation semiconductor devces in post-Moore's era.However,there still are some vital issues that need to be fully addressed in cation-based resistive switching device.Among them,the device performance degradation caused by reset failure phenomenon has in-creasingly been a bottleneck for further commercialization due to lack of clear physical mechanism and effective solution.To address above issues,this thesis focuses on the re-search of physical mechanism and effective solution to the reset failure phenomenon in cation-based resistive switching device.The main contents of this dissertation include:Chapter 2 gives a thorough literature review of the reset failure phenomenon and the current compromise solution in cation-based resistive switching device.Firstly,a re-view of the reset failure phenomenon and the possible mechanism occured in cation-based resistive switching device is given?section 2.2?.Subsquently,the current compromise so-lution to this reset failure phenomenon is reviewed?section 2.3?.And the advantages and disadvantages of these solutions is analyzed.In Chapter 3,the physical mechanism of reset failure phenomenon in cation-based resistive switching device is investigated.Firstly,various kinds of cation-based resistive switching devices are fabricated?section 3.2?.The reset failure phenomenon under DC and pulse voltage stimulus are studied comprehensively.And the results indicate that the reset failure phenomenon cannot be avoid by controlling the sweeping voltage?section3.3?.Furthermore,the micro-structure and composition of conductive filament?CF?in the Ag/ZrO₂/Pt device after reset failure phenomenon are analyzed.We found that the Ag CF not only bridge the insulating layer but also penetrate into Pt electrode?section3.4?.Finally,the switching mechanism of the reset failure phenomenon in cation-based resistive switching device are summarized as follows?section 3.5?.The negative-SET behavior,which can result in reset failure,is dominated by the reformation of the CF in cation-based resistive switching device.The CF overgrowth phenomenon will result in an active atoms”pool”in the counter electrode.And the”pool”of active atoms provide the cation source to reform the conductive filament in negative voltage bias.In Chapter 4,we proposed and studied a graphene barrier layer solution to elimi-nate reset failure phenomenon in cation-based resistive switching device.Firstly,various cation-based resistive switching devices with graphene barrier layer are designed and fab-ricated?section 4.2?.The micro-structure and composition of CF in Ag/ZrO₂/G/Pt device with graphene barrier layer are analyzed?section 4.3?.Through the comparision with the CF of Ag/ZrO₂/Pt device,the results demonstrate that the graphene interlayer has a good blocking effect on the CF overgrowth phenomenon.Furthermore,the electrical experi-ments and analysis of the various graphene-based resistive switching devices indicate that graphene barrier layer is an effective solution to eliminate the reset failure phenomenon induced by negatvie-SET behaviors.Finally,the comprehensive memory properties of the graphene-based devices are investigated?section 4.4?.In Chapter 5,we proposed and studied a TiN barrier layer solution to eliminate reset failure phenomenon in cation-based resistive switching device.Firstly,the TiN barrier layer devices integrated with Cu plug and transistor strucuture are fabricated?section 5.2?.The following characterization experiment demonstrate that the as-fabricated device has clear structure and the deposited film layer thickness is consistent with the design?section5.3?.The electrical experiments indicate that inserting the 5nm thickness TiN barrier layer is an effective way to eliminate the reset failure phenomenon.Furthermore,the switching performance of the TiN barrier layer device integrated with a transistor?1T1R device?are fully investigated under DC and pulse voltage stimulus.The results demonstrate the1T1R device has an amazing memory performance and has high potentiality for dense non-volatile memory array application?section 5.4?.