Research On Extensible Packet Switching Technology Based On Hardware And Software Co-operation

The emergence of new network protocol and rapid development of network application technologies posed new challenges on service carrying capabilities of network data plane.It demands to extend operations that support new protocols and packet processing without upgrading hardware.However,the data plane of existing network devices(such as routers and switches)implements packet processing based on ASIC chips or network processors.Due to rigid functions or programming difficulties,it is hard to provide open interfaces for the requirements of functional extension.With the development of multi-core CPU and high-capacity FPGA,the packet processing technologies based on multi-core CPU/FPGA attract a wide spread attention for being an effective way to extend functions of data plane.Whereas,it is difficult to promote CPU/FPGA processing platform without software/hardware joint packet processing model.In this paper,we make an intensive study of CPU/FPGA joint packet processing model and its key implementation techniques.The main work and innovations are as follows.1.Towards multi-core CPU/FPGA heterogeneous processing platform,we proposed ESA(Extensible Switching Architecture),a SW/HW tightly coupled packet processing model supporting functional extensions.In order to provide guidance to construct a CPU/FPGA packet processing platform,we presented the implementation model of key modules in ESA,the pipeline of SW/HW modules,the data interactive method between SW and HW modules and dynamic pipeline extension method based on NMI(Next Module Index)table.2.By analyzing the features of packet processing platform,we proposed a highefficiency buffer shared mechanism between CPU and FPGA named SDB(SelfDescribed Buffer)and designed SDB-DMA method based on this mechanism.SDB merges and compresses raw data and descriptor of a packet into consecutive buffer,which reduces the buffer management operations and the overhead of buffer allocation/deallocation efficiently.3.We proposed the implementation methods of programmable devices based on ESA switching model.By dividing the implementation of programmable devices into platform specific part and user specific part,we defined clean interface for the develop of customized functions.Besides,we proposed a new concept named FPGA OS to simplify the complexity of FPGA development.FPGA OS could provide multiple generic services for ESA hardware pipeline while hiding the heterogeneity of different FPGA platform.4.We implemented ESA prototype named iRouter based on Intel CPU and Altera FPGA.Besides,we designed several applications on iRouter by extending SW/HW module in pipeline,such as LISP forwarding,detection of source address spoofing and precise network monitoring.These experiments demonstrated the availability of ESA in SW/HW joint processing and function extensions.At present,our iRouter platforms have been widely deployed in many research institutions of Beijing,Nanjing and Changsha,playing a vital role in supporting the research of new network technologies.