Research On High Performance Packet Switching System Based On FPGA

With the further development of China's aerospace field and the continuous improvement of the speed and capacity of data transmission services,switching technology,as the center of gravity of communication network,shoulders the normal operation of the entire communication network task.In recent decades,packet switching has been widely used under the rapid development of Ethernet technology.But the traditional Ethernet switching technology can not achieve large capacity data exchange,so it is imperative to design a high speed and large capacity packet switching system.According to the relevant requirements of the school-enterprise cooperation project "Multiplex Packet Switching and Ground Test System",this paper designs and completes a packet switching system based on a shared buffer structure.This topic is based on FPGA as the platform design of high-performance packet switching system,the implementation of Ethernet protocol packet switching system,switching unit support 4 input ports and 4 output ports switching.Through the requirement analysis of the system,the specific scheme design is carried out.The work is as follows:Firstly,the 10-gigabit Ethernet high-speed interface and the internal structure of the system are studied in depth,and the packet switching system is designed by combining the relevant IP core encapsulated by Xilinx company with the internal logic of FPGA.It mainly includes the design of high-speed interface,packet processing and queue management module.And the design of the module combined with the specific implementation method is described in detail to ensure the feasibility of the design scheme.Finally,the design of the module is verified by simulation and board level verification,the function of the system is tested,and the problems encountered in the system are analyzed and solved.According to the results of software simulation and board level verification,it is shown that the designed system test is normal and meets the design requirements of packet switching unit.This paper presents a design scheme of 4×4 packet switching system based on FPGA.The information rate of each port can reach 10 Gbps.The improved shared cache structure is used to store and forward data,which improves the efficiency of data processing.Queue management uses linked list storage structure to store the corresponding address of data,and completes the scheduling of each port and priority queue by two-level scheduling algorithm based on polling mechanism,which improves the switching performance of the system.