Design Of Analog--Interface Circuit Used In Cyber-Physical Systems

The cyber- physical system(CPS)is used to realize real time perception,dynamic monitoring and timely feedback of large scale complex systems and wide area environments.Therefore,a large number of sensors and embedded controllers are needed to achieve real time signal acquisition and precise control of the system.For embedded controller,e.g.,the core modules include digital signal processor,wireless transceiver and analog interface circuit.The analog interface circuit,which processes different types of signals such as analog,digital and RF signals,has become a major design challenge.Study and design of low power,low cost,flexible and universal analog interface circuit is therefore of a great interest for the wide application of CPS.The proposed work mainly focus on the key design techniques as well as the silicon verification of these interface circuits.From the design considerations of low power consumption,low cost,flexibility and versatility,the specific research work of this article is as follows:(1)Research on large bandwidth variable gain amplifier with characteristics of dB- linearity gain control.The proposed variable gain amplifier achieves a large bandwidth and PVT robustness,which uses current replication technology,direct cascade technology and temperature compensation technology.Based on the proposed topology,a variable gain amplifier using resistive loads is implemented.Measurement results show that the proposed work exhibits a gain control range of41 dB,a dB linear error of 0.6 dB,and a bandwidth of 580 MHz.In order to reduce the effect of PVT variations,the variable gain amplifier based on active loads is implemented as well.The active load is able to reduce the impact of process and supply voltage on performance and a temperature compensation circuit is used to reduce the impact of temperature on performance.The test results show that the design with BJT has a gain control range of 51 dB,a dB linear error of 0.65 dB,and a bandwidth of 740 MHz.The gain control range of the active load variable gain amplifier based on the MOS in the offset subthreshold region is 45 dB and the dB linear error is 0.85 dB.In order to further reduce the influence of the process on the performance of the variable gain amplifier,an active load variable gain amplifier based on current shunt was studied and designed.Simulation results suggest that the circuit can change the bandwidth by changing the bias current.The gain control range can be further adjusted by changing the number of cascades.(2)Research and design of a 14 bit SAR ADC.In order to simplify the structure and reduce power consumption of the ADC,we use the superior board sampling technology and split capacitor structure,optimize the capacitor calibration algorithm and reduce the number of redundant capac-itors.The split capacitor structure is used to reduce a reference voltage and remove a reference voltage buffer,thereby reducing the overall power consumption of the circuit.In the optimized capacitance calibration algorithm,the switching between high end capacitors generates voltage er-rors and the low end capacitors are used to quantify the voltage errors to obtain the real weight of high end capacitors.The use of redundant bit capacitors can correct high bit comparison errors and simplify the capacitor calibration algorithm.The simulation based on Matlab shows that the capac-itance calibration algorithm can improve the SFDR of SAR ADC by 29 dB and SNDR by 23 dB.Simultaneously,the SAR ADC adopts the superior board sampling technology,which reduces the number of switching and further reduces power consumption.Based on the simulation in Cadence,the effective number of bits of the SAR ADC is 13.7 bit.(3)Research and design of core module in digital transmitter.?-? modulation technology has been used to implement a low- power and small- area RF digital to analog converter and an RF-DAC based on ?-? modulated 2 bit digital output is designed and measured.The test results show that the RFDAC based on ?-? modulated 2 bit digital output has problems of local oscil-lator leakage and nonlinearity.In order to further suppress the local oscillator leakage and reduce nonlinearity,an RFDAC based on ?-? modulated 1 bit digital output is designed.Moreover,the RFDAC can reduce noise by building a semi-digital FIR filter.In this thesis,a multi phase clock generator is designed using injection locked frequency divider with the two dimensional delay cells.The proposed multi phase clock generator can change the total phase delay to realize different di-vision ratios.In order to verify that the multiphase clock generator under study,the 4/5 frequency divider based on this structure is fabricated based on a standard 0.18 ?m CMOS process.The test results show that the operating frequency range of the 4/5 frequency divider is 4.8 to 6.2 GHz,the maximum power consumption is 0.5 m W,and the frequency division ratio can be accurately controlled.