Research On Key Technologies And FPGA Implementation Of PUF-based Key Generation

Physical unclonable function(PUF)is a promising hardware security technology,which extracts hardware fingerprints from the uncontrollable random manufacturing process variations of integrated circuits.The PUF-based key generation mechanism can provide high-security cryptographic key at a low cost for field-programmable gate array(FPGA)systems.In this paper,the research is mainly aimed at the key technologies and FPGA implementation of PUF-based key generator.First,for cryptographic key generation based on PUFs,it is very important to estimate the entropy of PUF responses accurately.The upper bound of the entropy estimated by compression algorithms is too losse,while the lower bound estimated by the min-entropy calculation is too conservative,especially when the sample size is small.The actual minentropy is between these bounds but is difficult to estimate accurately.In this paper,two models are proposed to estimate the convergence of the inter-chip min-entropy of PUF response.The basic idea is to find the relation between the expectation of the estimation result and the tested sample size and then predict the convergence of the min-entropy.The experimental results demonstrate that these two models can accurately estimate the convergence of the inter-chip min-entropy,and the prediction error is less than 0.01/bit for the tested static random-access memory(SRAM)chips.Second,since the application of PUF-based key generation generally requires a large amount of responses,it takes less hardware resources using arbiter PUF than other PUFs.However,one of the problems that an arbiter PUF implemented on FPGA platforms faces is the structural delay bias caused by asymmetric placement and routing.Aimed at this problem,a new tunable structure of arbiter PUFs is proposed.It is composed of programmable delay lines(PDLs)as main switch blocks,extra multiplexer(MUX)-based switch blocks as coarse tuning blocks,extra PDL-based switch blocks as fine tuning blocks.Based on these tuning blocks,an auto-tuning algorithm is designed and optimized to calibrate the delay bias.The experimental results on Xilinx Artix-7 FPGA platform show that the tuning algorithm can improve the bias of the responses of arbiter PUFs on FPGA platform and enhance the uniqueness of responses.The inter-chip Hamming distance of the responses can be increasd to approximately 49.6%.Third,the entropy of PUF responses is generally not high enough to meet the security requirement of key generation applications.Von Neumann extractor can impove the entropy of PUF responses,however the utilization rate of the responses is rather low.Aimed at this problem,an improvement method is proposed to collect as many responses,which are discarded in the extraction process,as possible to help correct the errors in the responses.Experimental results demonstrate that the utilization rate of the responses can be increased 2.5 times after applying the improvement method.Last,a practical structure of PUF-based key generator is proposed.The improved Von Neumann extractor is applied to the PUF responses to improve the min-entropy,then error correction codes are applied.Using this process method,it can be ensured that there is enough remaining entropy in the responses after error correction,while the entropy requirement of the raw responses is reduced.The key generation schemes are estimated based on SRAM PUFs and arbiter PUFs respectively.Then,a scheme based on arbiter PUF is implemented on an FPGA platform.The experimental results show that a secure,reliable and practical cryptographic key can be extracted using this scheme.